Research Bus Systems

Bus System

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Bus System

A bus is a communication system that connect several subsystems in a computer system. A typical computer system consist of several components i.e. Central Processing Unit (CPU), memory chips, and Input/output (I/O) devices. The bus system comprises of the linking media like wires and connectors, and a bus protocol. Buses can be categorized as serial or parallel and synchronous or asynchronous. The bus therefore lets the different components to communicate with each other by allowing information flows between units or devices.

The address lines show the source or terminus of the data on the data lines. Control lines are used in implementing the bus protocol. Regularly, there are lines to request bus control and to handle interrupts, etc. Status lines shows the advancement of the current transaction. Synchronous bus systems use clock signals to synchronize bus operations.

Bus Protocols

As a communication channel, the bus system is shared by many devices and hence rules have been established in order for the communication to happen appropriately. These established rules are called bus protocols. The architectural design of bus system contains several tradeoffs related to the breadth of the data bus, data transfer size, bus protocols, clocking, etc. Bus systems are categorized as synchronous and asynchronous buses depending on the whether the nus communications are controlled by a clock or not. There are parallel and serial buses depending on whether the data bits are sent on parallel wires or multiplexed onto one single wire.

Control of the bus communication in the presence of multiple devices necessitates defined procedures. Arbitration structures is essential in control of the bus communication in the existence of multiple devices. Below, different kinds of buses and arbitration structures are explained below.

Synchronous and Asynchronous Buses

In a synchronous bus, bus system processes are harmonized with reference to a clock signal. The bus system clock is usually derived from the computer system clock, though, it is often slower than the master clock. For example, 0.6GHz bus systems are used in computer systems with a processor clock of over 5GHz (Matthew, 2004). Bus systems are usually slower than processors because memory access times are typically longer than clock cycles of the processor. A bus transaction often takes a number of clock cycles, although the cycles are jointly referred as a bus cycle

According to Mueller & Zacker, (1988), an asynchronous bus system has no system clock. Handshaking is done to correctly conduct the communication of data between the sender and the receiver. For instance, in an asynchronous read operation, the bus system master sets the address and control signals on the bus system and then declares a synchronization signal. The synchronization signal from the master prompts the slave to get synchronized so that when it has accessed the data, it declares its own harmonization signal. The slave’s harmonization signal notifies the processor that there is legal data on the bus, and then it reads the data. This mode of harmonization is referred to as a full handshake. An asynchronous communication practice can be deliberated as a pair of Finite State machines (FSMs) that function in such a way that one FSM does not proceed until the other FSM has got to a certain state.

Serial and Parallel Buses

Parallel bus system are bus system that transfer several data bits at the same time. This category of bus system requires a wide buses because large chunks of data so that it can be transferred faster when multiple lines can be used. Parallel buses typically have 8, 16, 32 or 64 data lines. Parallel bus systems include: ISA, PCI, VESA, and EISA buses. (Mueller, S. & Zacker, C. 1988).

On the other hand, serial bus systems uses the same line to transfer different data bits of the same byte/word. Characteristically they have only one data line and the bits are flow one after the other, as a packet. An examples of series bus systems are The Universal Standard Bus (USB) and IEEE 1394 bus architecture. Parallel bus systems are more expensive than series bus system, although, parallel bus systems have higher throughput.

The figure is a diagram that showing the 8-bit AVR along with the data and address busses

Reference

Matthew, E. (2004). System bus. Retrieved from http://www.eastaughs.fsnet.co.uk/cpu/structure-bus.htm

Mueller, S. & Zacker, C. (1988). Upgrading and repairing PCs. Retrieved May 5, 2016 from http://www.pcguide/com/ref/mbsys/buses/types/agp-c.html